As computers have grown in complexity, the demand for more memory has grown. This in turn has led to a greater demand for higher density memories (memories capable of storing more bits of information in the same semiconductor surface area). In an attempt to increase the storage density of memories, the concept of a multi-bit memory cell was developed. More specifically, it was envisioned that if each memory cell were able to store more than one bit of data, then the storage density of the memory would be increased. Consequently, efforts have been made in recent years to develop memories using multi-bit memory cells. Most of the multi-bit memory cell work has been done in connection with DRAM memory cells.
In general, a multi-bit DRAM cell has the same construction as a single-bit DRAM cell, consisting of a storage capacitor and a cell gate. The difference between the multi-bit cell and the single-bit cell is manifested in the way the cells are used. To illustrate how a single memory cell can be used to store a plurality of bits of data, suppose that it is desirable to store two bits of data in a memory cell, and that the voltages to be stored in the memory cell range from 0 to 4 volts. In order to use the memory cell as a two-bit memory cell, the voltage range is first divided into four distinct voltage sub-ranges: (1) 0 to 1 volt; (2) 1 to 2 volts; (3) 2 to 3 volts; and (4) 3 to 4 volts. Each voltage sub-range represents a certain combination of two data bits. For example, the first sub-range can represent the data bits "00", the second sub-range can represent the data bits "01", the third sub-range can represent the data bits "10". and the fourth sub-range can represent the data bits "11". Once the voltage range is subdivided in this manner, two-bit data can be stored in the memory cell by applying and storing an appropriate voltage in the cell. For example, the data bits "10" can be stored in the memory cell by storing a voltage between 2 and 3 volts in the memory cell. Likewise, the data bits "11" can be stored in the memory cell by storing a voltage between 3 and 4 volts in the memory cell. Thus, by dividing the full voltage range into voltage sub-ranges, and then storing appropriate voltage levels in the memory cell, a single-bit memory cell can be converted into a multi-bit memory cell. This same concept can be extended to store three or more data bits per cell. In general, to store an n number of bits in a single cell, 2.sup.n distinct voltage sub-ranges will need to be created.
To maximize the information density of a memory, it is desirable to store as many bits of information in each cell as possible. In the prior art cells, two major factors have significantly limited the number of bits that can be stored in each cell. The first factor is noise. As noted above, to store more bits of information in a cell, more voltage sub-ranges need to be created. The more voltage sub-ranges that are created, the smaller the voltage separation between voltage sub-ranges becomes. At some point, the separation between sub-ranges becomes sufficiently small that noise signals can alter the data stored in the cell. Unless these noise signals are somehow reduced or canceled, they can seriously undermine the reliability of the data stored in the memory cell. Noise has been a serious and nagging problem in prior art memory cells.
Another major limiting factor is that of voltage range limitation. This limitation is caused by cell gate cut-off. To elaborate, a cell gate of a typical memory cell is an n-channel MOSFET. For this type of transistor, the resistance is given approximately by the following equation: EQU R.sub.FET .congruent.L/WK(V.sub.GS -V.sub.T),
where R.sub.FET is the resistance of the transistor, L is the length of the conducting channel, W is the width of the conducting channel, K is the transconductance parameter, V.sub.GS is gate-to-source voltage, and V.sub.T is the threshold voltage of the transistor. As can be seen from the above equation, as V.sub.GS approaches V.sub.T, the resistance of the transistor increases. Finally, the transistor will shut off when V.sub.GS becomes equal to V.sub.T. A point to note here is that the source of the transistor is coupled to the storage capacitor. Thus, the voltage at the source of the transistor is the same as the voltage stored in the capacitor. Since V.sub.GS is the voltage between the gate and the source terminal of the transistor, and since the source voltage is the same as the stored voltage, the higher the voltage stored within the capacitor becomes, the lower V.sub.GS becomes, assuming that the gate voltage remains fairly constant. At some point, the voltage stored in the capacitor becomes large enough that V.sub.GS is reduced to V.sub.T. At that point, conduction stops (i.e. the cell gate cuts off). It has been found that in typical memory cells designed to operate between 0 and 5 volts, cut-off occurs when the voltage stored in the capacitor reaches about 3.5 volts. As shown by this discussion, even though the operating voltage range is from 0 to 5 volts, the actual dynamic range of the memory cell is only from 0 to 3.5 volts. This cut-off effect significantly limits the dynamic range of the memory cell, which in turn limits the number of data bits that can be stored within the cell.
A similar effect is observed for p-channel cell gates, except that for p-channel cell gates, cut-off occurs below 1.4 volts. Thus, the dynamic range for a p-channel cell gate memory cell is between 1.4 volts and 5 volts. With either type of cell gate, the dynamic range of the memory cell is limited. In view of the shortcomings noted above for the prior art memory cells, an improved multi-bit memory cell is needed.